EDN

Efficient Testing of Analog/Mixed-Signal ICs using Verilog-A

Nitin Mohan received his B.Tech. in Electronics Engineering from Institute of Technology-BHU, India in 1999 and MA.Sc. in Electrical and Computer Engineering from University of Waterloo, Canada in ...
Design-Reuse

IP Configuration Management with Abstract Parameterizations

Abstract. This work presents the Configuration Manager for Abstract Parameterizations (CoMAP), an extensible tool set which is independent of hardware description or programming languages and ...
Design-Reuse

Guidelines for Verilog-A Compact Model Coding

The Verilog-AMS hardware description language [1] includes extensions dedicated to compact modeling, but does not define a reserved subset for compact modeling. This lack of specification combined ...
EDN

Assertion Methodologies for Verilog Design

Sometimes good ideas take a while to catch on in engineering practice. The use of in-line assertions to document assumptions and check for problems in RTL code is one such idea. Long ago proposed for ...
TechRepublic

8 Bit RISC Processor Using Verilog HDL

RISC is a design philosophy to reduce the complexity of instruction set that in turn reduces the amount of space, cycle time, cost and other parameters taken into account during the implementation of ...